In recent years, a multitude of so-called flash memories are used as a rewritable semiconductor memory device. The flash memory using a floating gate prevails among them, however, it is difficult for the memory of this type to allow a tunnel insulating film to be thinner, which is an obstacle for the mass storage. Hence, a multi-value memory cell is thought out, in which a threshold value of a transistor is varied by controlling a charge amount to the floating gate when writing, and multi-value data is allowed to be stored in one memory cell.
A new multi-value memory cell having an MNOS structure or a SONOS structure, different from the floating gate type memory cell, is proposed, which applies, to the gate insulating film just under a gate electrode, a two-layered structure of an oxide film/an nitride film (ON), namely, the structure that the nitride film is stacked on the oxide film as seen from a substrate, or a three-layered structure of the oxide film/the nitride film/the oxide film (ONO), namely, the structure that the nitride film and the oxide film are sequentially stacked on the oxide film seen from the substrate, and which stores the charge locally in the nitride film in the vicinity of respective source/drain of the transistor, resultingly storing 2-bits data with respect to one memory cell.
Such multi-value memory cell has a simpler structure than that of the floating gate-type memory cell, and has an advantage that a cell area per bit is about ½, compared with the floating-gate type memory cell. And further, a memory cell having a memory cell array structure and being advantageous to a miniaturization are studied, which does not have a contact hole for a bit line in each transistor even though it is a NOR type memory, by using a source/drain as a bit line (an embedded bit line), namely, by forming the bit line under a word line.
In the memory cell having the aforementioned MNOS structure or SONOS structure, in order to form the gate insulating film, first, after a thin lower oxide film (tunnel oxide film) having a film thickness of approximately 7 nm is formed by a thermal oxidation method, a nitride film having a film thickness of approximately 10 nm is deposited by a CVD method to form an ON film. In the case of the SONOS structure, an upper oxide film is further formed by thermally oxidizing an upper portion of the nitride film to form an ONO film in which the nitride film is sandwiched between upper and lower oxide films.
When the above-mentioned nitride film is formed by the CVD method, a heat of approximately 650° C. to 850° C. is applied. And further, in order to form the upper oxide film by the thermal oxidation of the nitride film, a heat treatment of 1000° C. or more is required. In addition, in order to form the high-quality lower oxide film, a temperature condition of 900° C. or more is required.
Accordingly, in order to form the ON film or the ONO film by the CVD method, there exists a problem that the high temperature heat treatment for a long time is fundamental and that a matching property is extremely low with respect to the miniaturization of a semiconductor element, especially a transistor, of a peripheral circuit region of a memory cell. In addition, in the memory cell structure to which an embedded bit line is used, an impurity of the bit line is diffused by the high temperature heat treatment. If the bit line is formed after the ON film or the ONO film is formed to avoid the diffusion, there is a problem that damage is generated in the ON film or the ONO film and the decrease of a withstand voltage is caused.
Since the nitride film (CVD nitride film) formed by the CVD method has many N holes constituting charge trap centers, the film is used for a charge trap film of the transistor of the MNOS structure or the SONOS structure and the like. However, the formation of the CVD nitride film requires the high temperature as described above, and further, in the case of the highly integrated MNOS structure or the SONOS structure and the like which stores 2 bits per cell by performing a charge injection only to respective edge portions of the source/drain switched between a read-out occasion and a rewrite occasion, the charge trap centers exist at portions where the charge injection is desired to be avoided in the nitride film in which the N holes are formed almost uniformly such as the CVD nitride film, so that inconvenience for a device operation is caused.
For example, if electrons are injected and stored to portions other than portions to which electrons or holes are injected and stored in the nitride film (in the vicinity of the edge of the drain), especially the center portion of a channel, there exists a problem that a threshold value of the transistor increases and a margin in the low state of threshold value decreases regardless of the injection state of the electrons or holes to the vicinity of the edge of the drain.
The present invention is made in view of the above problems and an object thereof is to provide a highly reliable semiconductor memory device and a manufacturing method thereof, in which a high quality nitride film is formed in a low temperature condition, in addition, the nitride film can be used as a charge trap film having a charge capture function sufficiently adaptable for a miniaturization and a high integration which are recent demands.